SRIGANESH CHANDRASEKARAN
( Broadcom )
Sriganesh Chandrasekaran is an R&D Staff Engineer at Broadcom, California, USA, recognized for his remarkable journey in the semiconductor industry and outstanding contributions to ASIC and AI hardware design. With over 12 years of expertise in ASIC design from RTL to GDS, he has played a pivotal role in developing complex ASIC, AI training and inference chips. His work in 2.5D/3D interposer integration and multi-die ASIC architectures has significantly advanced AI chip performance and efficiency.
As a key contributor to Broadcom’s world-first 3.5D XD-SiP technology, Sriganesh helped set new industry benchmarks in interconnect density, power efficiency, and high-performance computing. He has led efforts in power optimization, physical design methodologies, and automation workflows, accelerating AI chip production. His patent-pending innovation on scalable switched capacitor voltage regulators showcases his expertise in power management.
Honored in the DesignCon 40 Under 40 program (2024), Sriganesh continues to drive advancements in AI chip design, contributing to the global semiconductor industry and shaping the future of computing.
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ICST 2026 | IIT Patna, India | August 01-02, 2026