Mr. Vijayaprabhuvel Rajavel

Power-Efficient Semiconductor Testing: Making Chips Smarter and Testable

Abstract:

The increasing complexity of semiconductor devices has made efficient and reliable testing a crucial aspect of chip manufacturing. However, traditional test methodologies often result in excessive power consumption, impacting chip reliability, cost, and overall efficiency. This talk, "Power-Efficient Semiconductor Testing: Making Chips Smarter and Testable," explores Design for Testability (DFT) techniques that optimize semiconductor testing while minimizing power overhead. We will discuss key challenges in semiconductor testing and present practical solutions, including low-power scan testing, test pattern optimization, scan compression, and AI-driven adaptive testing strategies. These approaches help enhance test efficiency, reduce power dissipation, and improve yield without compromising test quality. By examining real-world industry applications and case studies, this session will highlight the impact of power-aware testing techniques in modern chip design. The talk will conclude with key takeaways and future trends in semiconductor test optimization, emphasizing how smart testing strategies contribute to more efficient and reliable semiconductor devices.

Brief Profile: 

Vijay is a Senior Member of IEEE with extensive experience in Design for Testability (DFT), semiconductor testing methodologies, and ASIC design. He has contributed to the development of DFT architectures, scan compression techniques, ATPG methodologies, and test automation frameworks, ensuring improved manufacturability and reliability of complex semiconductor devices. He has delivered invited talks, participated in multiple technical conferences, and contributed to industry and academic discussions on power-efficient testing and next-generation semiconductor test strategies.

Prior to his current role, Vijay served as a Lead Product Engineer at Cadence Design Systems, where he was responsible for developing and optimizing DFT methodologies, supporting key semiconductor customers, and resolving critical test challenges. In this role, he played a pivotal part in customer success, tool evaluations, and advancing test methodologies for high-performance computing and AI-driven semiconductor designs. Before joining Cadence, Vijay worked at Samsung Austin R&D Center,  where he developed advanced scan architectures, automated ATPG workflows, and enhanced test efficiency across multiple semiconductor projects.Earlier in his career, Vijay was a Hardware Test Engineer at Aricent, where he was responsible for the design, testing, and validation of analog and digital circuits for microcontroller-based systems. His work involved schematic design, PCB layout, board bring-up, and functional testing, contributing to the development of robust embedded systems. He also gained experience in hardware debugging, power analysis, and signal integrity validation, ensuring reliable performance in network connectivity solutions.

Vijay holds an M.S. in Electrical and Computer Engineering from Portland State University, USA, and a B.S. in Electronics and Communication Engineering from Anna University, India. His expertise and contributions have been recognized with multiple industry awards, including distinctions for DFT innovation, critical debug resolution, and semiconductor test automation advancements. Beyond his technical work, Vijay is actively involved in mentoring, peer reviewing, and knowledge-sharing initiatives. He has served as a reviewer and session chair for multiple IEEE and international conferences and is passionate about advancing semiconductor test strategies, low-power design methodologies, and AI-driven test automation frameworks.