Mr. Jayesh kumar pandey

In-System Test Architectures for Reliable AI and Robotic Systems-on-Chip

Abstract:
As AI and robotic systems demand higher reliability, In-System Test (IST) architectures enable scalable, on-chip diagnostics beyond traditional ATE methods. This talk outlines IST strategies for testing logic, memory, and interconnects throughout the SoC lifecycle. We’ll explore how IST improves field reliability, supports ISO 26262, and reduces debug time. Real-world examples highlight its application in robotics and autonomous platforms, with a brief look at emerging AI-driven test optimization.