Akhil Anand Gore

Scalable System-Level ESD Verification for 2.5D and 3D ICs Using a Reusable Multi-Die Static Analysis Framework

Abstract:

Advanced packaging technologies such as 2.5D interposers and 3D integrated circuits are enabling heterogeneous integration and high-bandwidth chiplet-based systems, but they introduce significant reliability challenges in Electrostatic Discharge (ESD) verification. In multi-die architectures, ESD discharge paths can span chiplets, micro-bumps, interposers, and through-silicon vias, requiring system-level verification beyond traditional die-level approaches. Conventional methods based on full database merging and parasitic re-extraction are often impractical due to technology incompatibilities, excessive memory usage, and long runtimes.

This work presents a reusable static verification framework that enables scalable system-level ESD analysis across topological connectivity, point-to-point resistance, and current density checks without requiring full layout merging. The methodology leverages chiplet-level verification reuse, structured metadata representation, and IEEE 3D-Blox-based stack connectivity modeling to construct cross-die discharge paths. A black-box abstraction allows chiplets to be treated as reusable verification components while preserving detailed debug capability when violations occur.

Experimental evaluation on representative multi-die systems demonstrates significant runtime improvements. For designs with 2 to 4 chiplets and 3,200 to over 6,200 interface bumps, verification runtime was reduced from 36 hours to 4.5 hours, 72 hours to 9.2 hours, and over 120 hours to 16 hours, respectively, achieving 6×–8× speedup. For larger configurations, approximately 7× runtime reduction was observed.

By eliminating redundant parasitic extraction and enabling modular verification workflows, this framework provides a scalable and practical solution for reliability verification in next-generation heterogeneous semiconductor systems.

Profile:

Akhil Anand Gore is a semiconductor engineering leader and subject-matter expert in Electronic Design Automation (EDA), with over a decade of experience developing and scaling reliability verification technologies for advanced process nodes, including 5nm and below. He currently serves as Manager of Product Engineering at Synopsys, where he leads a globally distributed team of engineers and architects delivering production-grade reliability verification solutions used by leading semiconductor companies.

Akhil has built his career at Synopsys, progressing from an intern to a leadership role through sustained technical contributions and recognized impact. He has led the conception, architecture, and deployment of Electrostatic Discharge (ESD) and reliability verification solutions that are certified by major foundries and integrated into customer tapeout workflows. As a primary technical authority in ESD verification, he collaborates closely with customers, foundries, and global field teams, while also influencing product direction across R&D, quality assurance, and product management.

His work includes foundational contributions such as architecting a unified static ESD verification platform, designing early verification architectures for 3DIC systems, and enabling major performance improvements in large-scale SoC simulations. Notably, his innovations have reduced simulation runtimes from over 20 days to approximately 2 days, significantly improving efficiency and enabling broader adoption of verification technologies. He has also led the development of certified ESD PDKs and created programming libraries that underpin global reliability verification workflows.

Akhil holds a Master of Science in Computer Engineering from North Carolina State University and a Bachelor of Engineering in Electronics from the University of Mumbai. He has received multiple recognitions at Synopsys, including a GM Quarterly Individual Award and a Synopsys Taiwan Team Award, reflecting his sustained technical leadership and contributions to industry-critical technologies.